1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor device in which data lines are separated by bank group and a method of driving the same.
2. Description of the Related Art
In general, a semiconductor device, such as Dynamic Random Access Memory (DRAM), performs a series of operations of storing or providing data when an operation of inputting and outputting data is requested by a controller, e.g., a central processing unit (CPU).
Furthermore, as the operating speed of a semiconductor system including a semiconductor device becomes fast and technology related to a semiconductor integrated circuit is advanced, a semiconductor device has been requested to input and output data at a faster rate. For this reason, additional circuits for improving performance when performing a data input/output (I/O) operation are gradually added to a semiconductor device.
In particular, there is a need for a multi-purpose register (MPR) in order to improve the performance of a semiconductor device when performing a data I/O operation. For example, in a Double Data Rate 3 Synchronous Dynamic Random Access Memory (DDR3 SDRAM), a multi-purpose register (MPR) has been used to support a read leveling operation. The read leveling operation is an operation of sending a data pattern, previously defined in a register of a memory chip, to a set of pins and controlling a skew of a data strobe signal DQS between a controller and the memory chip. Here, an operation for reading the data pattern stored in the register is performed irrespective of normal data stored in a memory cell. Accordingly, a kind of memory access operation, such as enabling a word line or precharging a bit line in order to read data patterns, is not necessary.
As described above, a multi-purpose register (MPR) in DDR3 SDRAM has been used to simply store predetermined data patterns. This is called a ‘Fixed Value Read-Out’ characteristic. In this characteristic, an additional operation for writing data, for example, MPR Write operation may not be necessary. For example, in a read leveling operation mode, i.e., MPR operation mode, predetermined pattern data, such as ‘10101010’, is uniformly outputted in response to a read command although a controller does not apply an active command to a memory chip, and thus a tuning task (tDS/tDH) for a high-speed operation between the controller and a memory chip may be performed.
In the next generation memory product group including DDR4 SDRAM, however, a method of writing a value of pattern data stored in and outputted from a multi-purpose register (MPR) in advance not a method of previously setting a value of the pattern data has been proposed. That is, the multi-purpose register (MPR) has a ‘Non-fixed Value Read-out’ characteristic not the existing ‘Fixed Value Read-out’ characteristic.
FIG. 1 shows a block diagram of a known semiconductor device.
Referring to FIG. 1, the semiconductor device 100 includes first to fourth global lines GIO_BG0<0:63> to GIO_BG3<0:63>, first to fourth bank groups BG0 to BG3 coupled with the first to fourth global lines GIO_BG0<0:63> to GIO_BG3<0:63>, respectively, an upper multi-purpose register MPR0, a lower multi-purpose register MPR1, an upper data output unit UDQ, and a lower data output unit LDQ. Each of the first to fourth global lines GIO_BG0<0:63> to GIO_BG3<0:63> includes a plurality of global lines and is electrically isolated from each other. The first to fourth bank groups BG0 to BG3 supply normal data to the plurality of first to fourth global lines GIO_BG0<0:63> to GIO_BG3<0:63> in a normal mode. The upper multi-purpose register MPR0 serves to supply multi-purpose data to the plurality of first global lines GIO_BG0<0:63> or the plurality of second global lines GIO_BG1<0:63> in an MPR operation mode. The lower multi-purpose register MPR1 serves to supply multi-purpose data to the plurality of third global lines GIO_BG2<0:63> or the plurality of fourth global lines GIO_BG3<0:63> in the MPR operation mode. The upper data output unit UDQ serves to externally output data loaded onto the first global lines GIO_BG0<0:63> or the second global lines GIO_BG1<0:63>. The lower data output unit LDQ serves to externally output data loaded onto the third global lines GIO_BG2<0:63> or the fourth global lines GIO_BG3<0:63>.
Each of the first to the fourth bank groups BG0 to BG3 includes a plurality of banks. The first and the second bank groups BG0 and BG1 are disposed in an upper memory area MA0, and the third and the fourth bank groups BG2 and BG3 are disposed in a lower memory area MA1. The upper memory area MA0 and the lower memory area MA1 are divided on the basis of a bank group on which a data transfer operation is performed depending on a data width option mode. For example, assuming that a maximum data width option mode supported by the semiconductor device 100 is an ‘X16 mode’, in the ‘X16 mode’, data outputted from the first bank group BG0 is externally outputted through eight upper pads (not shown) and simultaneously data outputted from the third bank group BG2 is externally outputted through eight lower pads (not shown), or data outputted from the second bank group BG1 is externally outputted through the eight upper pads and simultaneously data outputted from the fourth bank group BG3 is externally outputted through the eight lower pads. As described above, a memory area is divided into upper and lower memory areas depending on a data output method. Hereinafter, the first and the second bank groups BG0 and BG1 are referred to as first and second upper bank groups BG0 and BG1, and the third and the fourth bank groups BG2 and BG3 are referred to as first and second lower bank groups BG2 and BG3.
Furthermore, although not shown, the first to fourth global lines GIO_BG0<0:63> to GIO_BG3<0:63> are coupled with the plurality of banks included in the first to the fourth bank groups BG0 to BG3. For example, the first global lines GIO_BG0<0:63> are coupled with the plurality of banks, included in the first bank group BG0, in common. The second global lines GIO_BG1<0:63> are coupled with the plurality of banks, included in the second bank group BG1, in common. The third global lines GIO_BG2<0:63> are coupled with the plurality of banks, included in the third bank group BG2, in common. The fourth global lines GIO_BG3<0:63> are coupled with the plurality of banks, included in the fourth bank group BG3, in common. Meanwhile, the first and second global lines GIO_BG0<0:63> and GIO_BG1<0:63> are coupled with the upper multi-purpose register MPR0, the upper data output unit UDQ, and the lower data output unit LDQ in common, and the third and fourth global lines GIO_BG2<0:63> and GIO_BG3<0:63> are coupled with the lower data output unit LDQ and the lower multi-purpose register MPR1 in common. In this case, as described above, in a maximum data width option mode (e.g., X16 mode), data may be externally outputted through the upper data output unit UDQ and the lower data output unit LDQ, and in a data width option mode (e.g., X8 mode) other than the maximum data width option mode (e.g., X16 mode), data may be externally outputted through the lower data output unit LDQ only.
Furthermore, the upper multi-purpose register MPR0 is disposed in an upper peripheral area PAD that is closer to the upper memory area MA0 than to the lower memory area MA1. Furthermore, the lower multi-purpose register MPR1 is disposed in a lower peripheral area PA1 that is closer to the lower memory area MA1 than to the upper memory area MA0. For reference, circuits for providing multi-purpose data to be stored in the upper multi-purpose register MPR0 and the lower multi-purpose register MPR1 may be disposed in the lower peripheral area PA1. For example, a mode register set (MRS) circuit and a command & address parity (CAP) circuit may be disposed in the lower peripheral area PA1.
Furthermore, the upper data output unit UDQ externally outputs data loaded onto the first global lines GIO_BG0<0:63> or the second global lines GIO_BG1<0:63> only in a maximum data width option mode (e.g., X16 mode). Furthermore, the lower data output unit LDQ externally outputs data, loaded onto the third global lines GIO_BG2<0:63> or the fourth global lines GIO_BG3<0:63>, only in a maximum data width option mode (e.g., X16 mode), but externally outputs data, loaded onto the first to fourth global lines GIO_BG0<0:63> to GIO_BG3<0:63>, in a mode (e.g., X8 mode) other than the maximum data width option mode. Meanwhile, the upper data output unit UDQ and the lower data output unit LDQ are disposed in the upper peripheral area PA0.
The operation of the semiconductor device 100 configured as described above is described below. It is hereinafter assumed that a maximum data width option mode is an ‘X16 mode’.
First, the operation of the semiconductor device 100 in a normal mode is described.
When the X16 mode is entered, the upper data output unit UDQ externally outputs normal data, supplied by one of the first and the second upper bank groups BG0 and BG1, through the eight upper pads (not shown), and the lower data output unit LDQ externally outputs normal data, supplied by one of the first and the second lower bank groups BG2 and BG3, through the eight lower pads (not shown).
When an X8 mode is entered, only the lower data output unit LDQ is enabled, and thus normal data supplied by at least one of the first and the second upper bank groups BG0 and BG1 and the first and the second lower bank groups BG2 and BG3 is externally outputted through the eight pads.
A method of driving the semiconductor device 200 in an MPR operation mode is described below.
When the X16 mode is entered, the upper data output unit UDQ externally outputs multi-purpose data, supplied by the upper multi-purpose register MPR0, through the eight upper pads and the lower data output unit LDQ externally outputs multi-purpose data, supplied by the lower data output unit LDQ, through the eight lower pads.
The semiconductor device 100 having the above construction may have the following concerns.
The upper and lower multi-purpose registers MPR0 and MPR1 for providing multi-purpose data in the MPR operation mode are included in the upper peripheral area PA0 and the lower peripheral area PA1, respectively. In this case, in a maximum data width option mode, the multi-purpose data is loaded onto the first to fourth global lines GIO_BG0<0:63> to GIO_BG3<0:63> separated by bank group. However, there is a concern in that a large area may be occupied because the upper multi-purpose register MPR0 and the lower multi-purpose register MPR1 are included in the upper and lower peripheral areas. Furthermore, there is a concern in that an area occupied by the I/O lines of the upper and lower multi-purpose registers MPR0 and MPR1 may be increased because the I/O lines of the upper and lower multi-purpose registers MPR0 and MPR1 are expected to increase according to the number of the upper and lower multi-purpose registers MPR0 and MPR1.